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To ensure signal integrity circuit board design guidelines by big tree
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To ensure signal integrity circuit board design guidelines by BIG TREE
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| Article Posted: 07/26/2010 |
| Article Views: 19 |
| Articles Written: 1033 - MORE ARTICLES FROM THIS AUTHOR |
| Word Count: 1183 |
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To ensure signal integrity circuit board design guidelines |
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Business,Business News,Business Opportunities
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Signal integrity (SI) solve the problem sooner, the higher efficiency design, which can avoid the complete circuit board design to increase after the termination device. SI design planning tools and resources to many signal integrity This article explores the core issues and solve SI problems in several ways, this ignores the technical details of the design process.
1, SI of the problem With the IC output switching speed increase, no matter how the signal cycle, almost all design signal integrity problems are encountered. Even if you do not encounter the last issue of SI, but with increased frequency of the circuit, the future will face signal integrity issues. Signal integrity problems mainly refers to the signal overshoot and damped oscillation, which is mainly driven IC transition amplitude and a function of time. In other words, even if the routing topology has not changed, as long as the chip rate becomes fast enough, the existing design will also be in critical state or stop working. We use two examples to illustrate the signal integrity design is inevitable.
One example? In communications, telecommunications companies are cutting-edge voice and data exchange for the production of high-speed circuit board (above 500MHz), then the cost is not particularly important, so you can maximize the use of multilayer boards. This circuit board can achieve full ground and constitute a power supply circuit can also be used according to need a lot of discrete termination devices, but the design must be correct, not in a critical state. SI and EMC experts in wiring prior to simulation and calculation, then, circuit board design can follow a series of very strict design rules, where in doubt, can increase the termination devices, to gain as much safety margin of SI volume. Actual work process board always some problems, for which client connection through the use of controlled impedance, SI problems could be avoided. In short, the super-standard design can solve SI problems.
Examples of the two? From cost considerations, the circuit board is usually limited to less than four (which are the two power planes and ground layer). This greatly limits the role of impedance control. In addition, the wiring layer increased crosstalk Major General, while the signal line spacing must be the minimum to put more cloth printing line. On the other hand, design engineers must use the latest and greatest CPU, memory and video bus designs must consider the issue of SI. On the wiring, topology and termination methods, engineers can usually get from a lot of CPU manufacturer recommends, however, these design guidelines is also necessary to integrate with the manufacturing process. To a large extent, the circuit board designer than a telecommunications designer's work more difficult, because the increase in impedance control and the termination device is very little room. Time to fully study and solve those who do not complete the signal, while ensuring that product design period. Here are the SI design process design for the universal.
2, design of preparation before Before the start of the design must first consider and determine the design strategy, so as to guide the choice of such components, circuit board manufacturing process selection and cost control and so on. The SI, in order to conduct research in advance to form a plan or design guidelines to ensure that the design result is not apparent in the SI issue, crosstalk or timing problems. Some design criteria can be provided by the IC manufacturer, however, chip suppliers to provide guidelines (or your own design guidelines) there are some limitations, according to this fundamental design criteria may not satisfy the requirements SI board. If design rules are easy to design engineers also do not need a. Before the actual routing, we must first solve the following problem, in most cases, these problems will affect the design you are (or are considering design) of the circuit board, if the large number of circuit boards, this work is valuable.
3, the circuit board stack Some of the project team on the PCB layers have great autonomy in the determination, while others have no such autonomy to the project team, therefore, to understand your position is very important. Engineers and manufacturing and cost analysis can determine the circuit board stack communication error, then discovered that the circuit board manufacturing tolerances of the opportunity. For example, if you specify a particular layer is 50 impedance control, the manufacturer how to measure and to ensure that the value it? Other key issues include? What is the expected manufacturing tolerances? The insulation of the circuit board is expected to what is constant? Line width and spacing of the allowable error is much? Ground plane and signal layer thickness and spacing of the allowable error is how much? All this information can be pre-routing phase. According to the data, you can choose to stack up. Note that almost every other circuit board or back into the PCB has a thickness requirements, and most circuit board manufacturers can produce different types of layer thickness is fixed, this would greatly constrained the number of the final stack . You may want to work closely with manufacturers to define the number of cascading. Impedance control tool should be used to generate target impedance range of different levels, be sure to take into account the manufacturer's manufacturing tolerances and the impact of adjacent wiring. Ideally, the signal integrity, all high-speed wiring in the impedance control node should be the inner layer (for example, stripline), but in reality, engineers must use all or part of the outer layer for routing high-speed node. For SI the best and keep the circuit board decoupling, it should be possible to ground level / power planes in pairs laying. If you can only have a butt ground / power planes, you only will the. If there are no power levels, according to the definition of SI problems you may encounter. You may also encountered such a situation, that is not defined until the signal return path is difficult to simulation or emulation board performance.
4, crosstalk and impedance control
Coupling from adjacent signal lines will lead to changes in the signal line crosstalk and impedance. Adjacent parallel signal lines coupling between signal lines, or may decide to various types of signal lines between the "security" or the expected distance (or length of the parallel wiring). For example, the node wishing to clock the data signals within 100mV of crosstalk limit, have to signal to maintain the parallel alignment, you can calculate or simulation, found at any given level of signal wiring between the minimum allowable spacing. At the same time, important if the design contains impedance node (or a clock or a dedicated high-speed memory architecture), you have to be placed in the floor wiring I am an expert from China Manufacturers, usually analyzes all kind of industries situation, such as plate warmer , ceramic glass cooktop.
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