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"The amount of design wins and early adoptions are ahead of wherewe expected them to be," says Gavrielov. "We're definitely ahead of plan in terms of yield," adds Gavrielov,"we're not seeing yield issues on HPL. It's a high k metal gateprocess but it's a less complex process than the HP process - ithas less mask steps." He attributes the high yields to the "very intimate" linkage inprocess development with TSMC and to the decision Xilinx made to use TSMC's HPL processrather than the LP and HP processes chosen by companies which havestruggled. He adds that there are aspects of the HP process which Xilinx'sengineers considered to be riskier than the HPL process. "We dodged some of the challenges other companies haveencountered," says Gavrielov. Nvidia, Qualcomm and Altera have all complained about shortages ofsupply from TSMC. Gavrielov concedes that: "TSMC may have under-estimated capacityrequirements but they're scrambling to fix that." Xilinx has just started sampling its 28nm heterogeneous 3D stackedVirtex-7 and is shipping volume 'thousands of units' of itshomogeneous 3D stacked part. Homogeneous means it only has FPGA slices; heterogeneous means ithas FPGA slices plus transceivers. The Virtex 7 has16 28Gbps transceivers and 72 13.1Gbpstransceivers. The die sit side by side on an interposer connectedby TSVs. "It has much higher bandwidth than you can achieve with an FPGA,"says Gavrielov. Xilinx's high hopes for the 3D part derive from the tools. "It's not just the TSVs and it's not just the architecture of thesilicon or the packaging - the big enabler is the software," says Gavrielov, "that's whywe're so excited by Vivado (the design suite) - because we have aunique advantage because we provide the tools. Vivado's taken 1000man-years to develop. With the tools you can achieve things whichwould be very difficult to do with commercial tools. We provideVivado to customers as a cost of doing business. Anyone who buysthe chip gets the software." "In July, Vivado will be made broadly available to our entirecustomer base." When it is made broadly available, Vivado will include the toolsfor programming FPGAs in C. Xilinx acquired the technology when it bought AutoESL. Do customers use it? "Absolutely," replies Gavrielov, "they'regetting fabulous results. They're getting results which customerssay are better optimised than hand-crafted designs." "It's revolutionary in terms of time to market and it broadens themarkets we address," says Gavrielov, "it allows a lot of designerswho are not FPGA heavyweights to use FPGAs. It allows otherdesigners to get the benefits of an optimised FPGA solution. So itbroadens our user base." The C programmable tool works for all Xilinx's parts at the 28nmnode and will be integrated into the Vivado programme when it goesto all Xilinx's customers in July. Another thing which 28nm brings to the party is low-cost SOC. Herethe company has come out with Zynq which has a brace of ARM CortexA9s, DSPs, and virtually any peripheral you want. "It's the biggest deal," says Gavrielov, "it allows us to move fullforce into SOC. It's low power, it's low cost it has all theadvantages of SOC design without the cost. Moving to 28nm means wecan do amazing things - it's an SOC but it's all programmable - thesoftware, the hardware and the I/O." "It could be done in the past but it was too expensive," addsGavrielov, "now, with 28nm, we can attack a lot of applicationshead on. For instance automotive is very cost-conscious. Wecouldn't get within a hundred miles of an automotive SOC. Now wecan." "At 28nm we're taking a lot of share from ASICs and ASSPs,"concludes Gavrielov, "we expect the FPGA market to continue to growfaster than the ASIC and ASSP markets. We expect market growth of8-12% CAGR between 2011 and 2020 - so by 2020 it should havedoubled in size from today's $5bn.". I am an expert from opticalfiberpatchcord.com, while we provides the quality product, such as Optical Fiber Connectors Manufacturer , Optical Fiber Splitter Manufacturer, Fiber Optic Terminal Box,and more.
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